Method to improve charge pump reliability, efficiency and size

ABSTRACT

A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

DESCRIPTION BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to semiconductorstructures and, more particularly, to a method to design a low-cost,high-performance charge pump system.

[0003] 2. Background Description

[0004] In semiconductor capacitor structures, oxide reliability concernbecomes more and more severe as the oxide thickness is further scaleddown. Capacitor dielectric used in “high-stress” circuits could sufferdielectric breakdown if the devices are not properly protected. Ageneral guideline for the dielectric reliability is shown in FIG. 1. Ifthe thickness of the dielectric for a technology is chosen to be 55 nm(the vertical dash line), then for gate or capacitor devices with 10 mm²area can sustain a voltage V1 (about 2.2 volts) maximum use voltagewithout having a reliability concern. The smaller the over-all devicearea, the higher sustainable stress voltage is allowed for the device.On the other hand, the thinner the dielectric layer thickness the lowerthe stress it can sustain for a given surface area. In a DRAM (dynamicrandom access memory) chip, many different kinds of charge pump circuitsare required to provide different internally generated voltage levels.These pump circuits usually are equipped with several different sizedboost capacitors made by planar capacitors. When the number of the pumpcircuits are increased, and the size of the boost capacitors used in thepump circuits, the reliability of the capacitor dielectric becomes aconcern, especially for those capacitors operated at high voltagelevels.

SUMMARY OF THE INVENTION

[0005] It is therefore an object of the present invention to provide amethod to resolve the capacitor dielectric problem in a charge pumpsystem.

[0006] It is another object of this invention to significantly reducethe pump size

[0007] It is yet another object of the invention to improve the pumpefficiency and capacity.

[0008] According to the invention, there is provided a dynamic clampused in conjunction with capacitors with deep trench capacitors or otherhigh-density capacitors, such as high-k dielectric and three dimensional(3D) stack capacitors. The dynamic clamp is realized using a two stagepump operation cycle such that, during a first stage pump cycle, amiddle node of a pair of series connected capacitors is pre-charged to asupply voltage and, during a second stage pump cycle, the middle node iscoupled by a boost clock. Thus, at any moment in the pump operationcycle, the voltage across the capacitors is held within a safety range.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0010]FIG. 1 is a graph showing the maximum use voltage as a function ofoxide thickness and surface area;

[0011]FIG. 2 is a schematic circuit diagram of a prior art charge pumpcircuit;

[0012]FIG. 3 is a timing diagram of the charge pump circuit of FIG. 2;

[0013]FIGS. 4A and 4B are layout plans, respectively, for the existingcharge pump and a charge pump according to the present invention;

[0014]FIG. 5 is a schematic circuit diagram of a dynamic voltageclamping circuit used to clamp the intermediate node of two capacitorsconnected in series;

[0015]FIG. 6 is a timing diagram showing the operation of the clampingcircuit of FIG. 5;

[0016]FIG. 7 is schematic circuit diagram of the charge pump circuitusing deep trench capacitors according to a preferred embodiment of theinvention;

[0017]FIG. 8 is a graph showing the difference in the ramp-up ratesbetween the old and new charge pump circuits;

[0018]FIG. 9 is a graph showing the difference between the currentsupply capacity of the new and old charge pump circuits;

[0019]FIGS. 10A, 10B and 10C are waveforms showing, respectively, thevoltage stress of the first capacitor, the second capacitor and, forcomparison, a single capacitor, respectively;

[0020]FIGS. 11A and 11B are waveforms of voltage stress across the firstcapacitor and the second capacitor, respectively for dynamic clampingwith Vint supply;

[0021]FIGS. 12A and 128 are waveforms of voltage stress across the firstcapacitor and the second capacitor, respectively, for dynamic clampingwith Vblh supply; and

[0022]FIGS. 13A are waveforms of pump output voltage comparison betweendynamic and static clamps, and FIGS. 13B and 13C are, respectively,waveforms of the voltage stress across the first and second capacitorsin the static clamp situation.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0023] The invention is a method to prevent dielectric breakdown ofsemiconductor capacitor structures under excessive voltage stress. Morespecifically, the method according to the invention prevents dielectricbreak down of boost capacitors of a charge pump circuit as an example. Amodem charge pump is illustrated in FIG. 2. Usually several differentsized capacitors, C1, C2, C3, C4, etc., are used to boost the outputvoltage efficiently. The capacitor size varies from 50 Fm² to 4500 Fm².Normally, in each DRAM chip, up to forty pumps may be employed.Therefore, the overall stress area can be significant, and the breakdownprobability is relatively high.

[0024] The pump has a symmetrical design. The upper portion of thecircuit and the lower portion of the circuit are mirrored to the centerline. An oscillator and a timing circuit (not shown) are used togenerate the clocked boosted signals, BOOTA, BOOTB, etc. During thefirst half clock period, the upper portion of the circuit pumps thecharge from supply to output, while during the second half period, thelower portion of the circuit continues the pump action. The detailedpumping sequence is like this. During a pre-charge period, the nodes A1,B1 are pre-charged to the supply voltage, or Vcc. In other words, thecharge is first drawn from the supply to the A1 node. When BOOT1A clockapplies a pulse from ground to Vcc on capacitor C1, the other node A1gets boosted to 2 Vcc. At the same time, node A1 a on capacitor C2 isalso boosted to 2 Vcc from its pre-charge level of Vcc. This will keepthe nodes B1 a and B1 both at Vcc and ready for the second half cycle ofpumping. When the A1 node is boosted to 2 Vcc, the BOOT3A clock booststhe A3 node from 2 Vcc to 3 Vcc while maintaining the B3 node at 2 Vcc.At this point, the A2 node is first boosted up from Vcc to 2 Vcc. Butwhen the A3 node drops from 2 Vcc to Vcc, BOOT2A clock continues toboost the A2 node from 2 Vcc to 3 Vcc. Notice that all the levelsmentioned above experience a nMOS (n-type Metal Oxide Semiconductor)device threshold voltage (Vthn) drop. The final voltage level of node A2will reach to (3Vcc-Vthn). The charge is thus drawn from node A1 toVout. During the next pump cycle, charge is pumped from Vcc to node B2,and then from node B1 to Vout.

[0025] This alternate pumping action allows the pump to have a highefficiency. During the first cycle of pump action, the charge is storedin capacitor C1. Therefore, capacitor C1 will not suffer excessivestress. Since capacitor C2 is used to maintain the voltage of nodes A1 aand B1 a, this capacitor also will not suffer excessive stress. On theother hand, the boost capacitor C3 will experience excessive stressbecause the node A2 gets boosted from Vcc to 3 Vcc. The capacitor C3requires special attention so that it will not break down or suffer anykind of degradation during the life time of the pump. Currently, thecapacitors are formed by thick oxide planar structure, which results ina large layout area as shown in FIG. 4A.

[0026] The timing diagram of the pump circuit is shown in FIG. 3. Whenthe clock BOOST1A is pulsed from ground to V1, both nodes A1 and A1 aare boosted from V1 to V2. In the meantime, the clock BOOST3A is pulsedfrom ground to V1 which boosts the node A3 up from V2 to V3 accordingly.The clock pulse of BOOST2A is then up from ground to V1 and subsequentlynode A2 gets boosted from V1 to V2 then to V3. The voltage stress acrossthe capacitor C4 between node BOOST3A and node A3 is basicallymaintained within one Vcc. Similarly, the node stress across capacitorsC1 and C2 are all at about one Vcc. However, the voltage stress acrosscapacitor C3 between nodes BOOT2A and node A2 will be at least 2 Vcc.

[0027] A dynamic voltage clamping circuit shown in FIG. 5 is used toclamp the intermediate node of two serially stacked capacitors. Asmentioned, the pump is designed in a symmetrical way. When the upperportion of the pump is in a pumping action, the lower portion is in apre-charging action, and vice versa. In order to reduce the high voltageacross the problematic capacitors, we stack the capacitors in series.For example, the upper capacitor C3 can be formed with two capacitors inseries, each twice the size as before. Therefore, the effectivecapacitance value is maintained the same. The two intermediate nodes Amand Bm are now clamped firstly by diodes of N1 and N2, respectively.Therefore, during power-on, these two nodes will be pre-charged to(Vcc-Vthn), or an nMOS device's threshold (Vthn) lower than the supplyvoltage (Vcc) level. These two intermediate nodes Am and Bm are clampedalso by cross-coupled nMOS transistors N3 and N4. During pump operation,the voltage levels of Am and Bm nodes are alternatively charged andboosted according to the pump clock cycle. In other words, during eachpump cycle, when the clock at node A1 is high, the clock at node B1 mustbe low, and vice versa. When the clock at node A1 is boosted, theintermediate node Am is coupled up, at the same time intermediate nodeBm is pre-charged to (Vcc-Vthn). The waveforms of the clocks and theintermediate voltages are shown in FIG. 6. During the next cycle, theintermediate node Bm is coupled up with the B1 clock, while theintermediate node Am is pre-charged. With this arrangement, the voltageacross any of the capacitors is restricted within a safety range withoutaffecting the pump efficiency.

[0028] A straight-forward approach is to clamp nodes Am and Bm using areference voltage, also called the static clamp method. There are twodisadvantages with is approach. First, the reference voltage must beprovided using a circuit which is much bigger in size than the clampingdevices described here. Second, the static clamping is not as efficientas the dynamic clamping. The reference voltage tends to clamp both nodesAm and Bm at the fixed level at all times. If the reference voltage isnot strong enough, the voltage across the capacitor can exceed thesafety limit. On the other hand, if the reference voltage level is toostrong, the pump efficiency will be degraded.

[0029] The supply voltage level must be carefully chosen in order todynamically adjust the Am and Bm voltages to be in the middle of themaximum voltage range. We propose to use Vin (or about 1.9V) for thecapacitor C3, and Vblh (or about 1.6V) (Vblh is an internally generatedvoltage for DRAM bit line operation) for the capacitor C2 clamping. Inorder to save the pump layout area, any existing on-chip high densitycapacitor can be used as the boost or reservoir capacitors for the pump.These capacitors include a deep trench capacitor, three-dimensional (3D)stacked capacitors, or a capacitor with high-k dielectric constant, etc.A layout of the same charge pump using deep trench capacitors is shownin FIG. 4B. The total size of the pump including extra capacitors neededto stack them is still less than one quarter the original layout shownin FIG. 4A. The use of deep-trench capacitors for the boost capacitor ofthe charge pump circuit requires no extra cost to process.

[0030] In FIG. 7, the schematic of a pump circuit using deep trenchcapacitors is shown. In this schematic diagram, parasitic capacitors,such as the capacitance due to P-well and plate, etc., are all includedin the simulation and evaluation and will be discussed more later. Thefirst embodiment is to replace all the planar capacitors with deeptrench capacitors to save the area. The second embodiment is to replaceonly those with large size capacitors, such as capacitors C1 and C3. Tooptimize the performance, we are able to further increase the capacitorsize which was forbidden due to area constraints when using planar typecapacitors, for example, the size of capacitor C1 is doubled. Tooptimize the reliability protection, we keep the ratio of two stackeddeep trench capacitors sizes of C3 and C4 to be in the ranges 1:2 to 1:3so that the voltage stress across the two capacitors will be distributedmore evenly.

[0031] For example, capacitor C3 is now replaced with two deep-trenchcapacitors connected in series. Note that each deep-trench capacitor isformed by a group of small deep-trench capacitors identical to those inthe cell of the memory array and connected in parallel. Cross-coupledboosted devices N4, N5 are used to dynamically clamp the intermediatenode between two deep-trench capacitors. Precharge devices N1 and N2 areused to pre-charge the same nodes during power-on. A similar arrangementis made for capacitor C4 as shown in FIG. 7.

[0032] The pump strength is improved significantly. The ramp-up ratebetween the new and the old pumps are shown in FIG. 8. Within 1000 nsthe new pump with deep trench capacitors will reach 4.3V, while the oldpump with planar capacitors reaches only 4V. The current supply capacityof the new pump is 26% better than the old pump, as shown in FIG. 9. InFIG. 9, the upper two waveforms (A) and (B) are the Vout of the chargepump using deep-trench capacitors as the boost capacitor. Waveform (A)is the Vout waveform when the charge pump is constantly withdrawing aload of 3.1 mA, while waveform (B) is Vout with a load of 3.6 mA. On theother hand, waveforms (C) and (D) are Vout waveforms of a charge pumpusing a conventional planar capacitor as the boost capacitor. Waveform(C) is Vout when the output load is 3.1 mA, while waveform (D) is whenthe output load is 4.1 mA. Since the planar boost capacitor is smallerthan that of the deep-trench capacitor, the charge pump capacity ispoorer.

[0033] The voltage stress across the capacitors are compared. First, weuse Vext (2.5V) to clamp the intermediate nodes Am and Bm. FIGS. 10A and10B are the voltage stress across each of the two stacked deep trenchcapacitors, i.e., 1V and 3.05V. Compared to that across a single planarcapacitor of 3.88V, the reliability improvement is obvious. But we arenot satisfied with the results, since 3V, actually 2.5V with 100% dutycycle, is still too high for the deep trench capacitors. In FIG. 11, weuse Vint (1.9V-2.1V) to clamp the capacitors. The results aresatisfactory, the maximum capacitor stress is now less than 2.0V. InFIG. 12, the clamp voltage is further reduced to Vblh (1.6V), and themaximum stress is now limited below 1.76V. Without using high densitydeep-trench capacitors, the size of the pump will be significantlyincreased by using two capacitors in series. Since when connecting themin series, each capacitor size is physically increased by four times.

[0034] The result of dynamic clamp technique is compared to that of astatic clamp Here, the static clamp is formed by using a wide channellength of pMOS device (L=3 Fm, W=1 Fm) to tie the intermediate node tothe Vcc supply. Under the identical condition, the dynamic clamptechnique results in more pumping efficiency. As shown in FIG. 13A, thepump with dynamic clamp has a stronger pumping power In FIGS. 13B and13C, the static clamp shows 0.1V higher voltage stress on one of thestacked deep trench capacitors.

[0035] To form a large capacitor using a deep trench capacitor has beendemonstrated. It has been used to form large size on-chip decouplingcapacitor. But it has never been used in the active components before.For the deep trench capacitor to be used as the boost capacitors in thecharge pump, one major concern is the parasitic effect on pumpperformance. These parasitic components include plate resistance, trenchresistance, strap resistance, channel resistance, parasitic capacitanceplate to well, plate to substrate, etc. During charge pump performancestudy, these undesirable parasitic components were included in thesimulation. Our study concludes that a simplified trench capacitor modelcan be used to represent the full trench capacitor network, includingall the mentioned parasitic components. It suggests that the modelshould have a 30 kS resistor connected in series to each cell capacitor.

[0036] Other than deep-trench capacitors, other high-density capacitors,such as high-k dielectric and 3D stack capacitors, can be employed in asimilar way to avoid high oxide stress while improving charge pumpefficiency in the practice of the invention. This invention only focuseson the charge pump circuit since the voltage stress is a dynamic stressand a cross-coupled pre-charge device can be easily provided to clampthe intermediate node of two capacitors in series.

[0037] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims

Having thus described our invention, what we claim as new and desire tosecure by Letters Patent is as follows:
 1. In a semiconductor chargepump circuit including at least one high stress boost capacitor, theimprovement comprising: at least one pair of boost capacitors connectedin series replacing the high stress boost capacitor and each having acapacitance at least two times the high stress capacitor; and at leastone dynamic clamping circuit used in conjunction with the pair of boostcapacitors, the dynamic clamp being realized using a two stage pumpoperation cycle such that, during a first stage pump cycle, a middlenode of the pair of series connected capacitors is pre-charged to areference voltage and, during a second stage pump cycle, the middle nodeis coupled by a boost clock whereby, at any moment in the pump operationcycle, the voltage across the capacitors is held within a safety range.2. The semiconductor charge pump circuit of claim 1, wherein the pair ofcapacitors are high-density deep trench capacitors.
 3. The semiconductorcharge pump circuit of claim 1, wherein the pair of capacitors are highdielectric constant capacitors.
 4. The semiconductor charge pump circuitof claim 1, wherein the pair of capacitors are 3D high-densitycapacitors.
 5. The semiconductor charge pump circuit of claim 1, whereinthe charge pump circuit is incorporated in a dynamic random accessmemory (DRAM) array and the pair of capacitors are a same type ofcapacitor used in cells of the DRAM array
 6. The semiconductor chargepump circuit of claim 5, wherein each of the pair of capacitors areformed by a plurality of capacitors of the same type of capacitor usedin cells of the DRAM array, the plurality of capacitors forming each ofthe pair of capacitors being connected in parallel.
 7. The semiconductorcharge pump circuit of claim 1, wherein the reference voltage issupplied by an externally generated supply voltage.
 8. The semiconductorcharge pump circuit of claim 1, wherein the reference voltage is aninternally generated voltage.
 9. The semiconductor charge pump circuitof claim 1, wherein an area ratio of the pair of capacitors is such thatvoltages across each capacitor are evenly distributed.
 10. Asemiconductor charge pump circuit comprising: a first capacitorconnected between a first clock terminal and a first node; a pre-chargecircuit connected to said first node for pre-charging said first node toa supply voltage; means for applying a pulsed voltage equal to saidsupply voltage to said first clock terminal thereby boosting a voltageat said first node to twice the supply voltage; a pair of boostcapacitors connected in series between a second clock terminal and asecond node, said pair of boost capacitors replacing a high stress boostcapacitor and each having a capacitance at least two times the highstress capacitor; at least one dynamic clamping circuit used inconjunction with the pair of boost capacitors, the dynamic clamp beingrealized using a two stage pump operation cycle such that, during afirst stage pump cycle, a middle node of the pair of series connectedcapacitors is pre-charged to a reference voltage and, during a secondstage pump cycle, the middle node is coupled by a boost clock whereby,at any moment in the pump operation cycle, the voltage across thecapacitors is held within a safety range; a pass gate connecting saidfirst node to said second node, means for pulsing said pass gate toboost said second node to twice the supply voltage; and means forapplying a pulsed voltage equal to said supply voltage to said secondclock terminal thereby boosting a voltage at said second node toapproximately three times the supply voltage.
 11. The semiconductorcharge pump circuit of claim 10, wherein the pump circuit has asymmetrical design and further comprises: a second capacitor connectedbetween a third clock terminal and a third node; a second pre-chargecircuit connected to said third node for pre-charging said third node toa supply voltage; second means for applying a pulsed voltage equal tosaid supply voltage to said third clock terminal thereby boosting avoltage at said third node to twice the supply voltage; a second pair ofboost capacitors connected in series between a fourth clock terminal anda fourth node, said second pair of boost capacitors replacing a highstress boost capacitor and each having a capacitance at least two timesthe high stress capacitor; a second dynamic clamping circuit used inconjunction with the second pair of boost capacitors, the second dynamicclamp being realized using a two stage pump operation cycle such that,during a first stage pump cycle, a middle node of the second pair ofseries connected capacitors is pre-charged to a reference voltage and,during a second stage pump cycle, the middle node is coupled by a boostclock whereby, at any moment in the pump operation cycle, the voltageacross the capacitors is held within a safety range; a second pass gateconnecting said third node to said fourth node, second means for pulsingsaid second pass gate to boost said fourth node to twice the supplyvoltage; and second means for applying a pulsed voltage equal to saidsupply voltage to said fourth clock terminal thereby boosting a voltageat said second node to approximately three times the supply voltage,whereby an alternate pumping action is realized by the symmetricaldesign of the charge pump circuit.
 12. The semiconductor charge pumpcircuit of claim 10, wherein the pair of capacitors are high-densitydeep trench capacitors.
 13. The semiconductor charge pump circuit ofclaim 10, wherein the pair of capacitors are high dielectric constantcapacitors.
 14. The semiconductor charge pump circuit of claim 10,wherein the pair of capacitors are 3D high-density capacitors.
 15. Thesemiconductor charge pump circuit of claim 10, wherein the charge pumpcircuit is incorporated in a dynamic random access memory (DRAM) arrayand the pair of capac are a same type of capacitor used in cells of theDRAM array.
 16. The semiconductor charge pump circuit of claim 15,wherein each of the pair of capacitors are formed by a plurality ofcapacitors of the same type of capacitor used in cells of the DRAMarray, the plurality of capacitors forming each of the pair ofcapacitors being connected in parallel.
 17. The semiconductor chargepump circuit of claim 10, wherein the reference voltage is supplied byan externally generated supply voltage.
 18. The semiconductor chargepump circuit of claim 10, wherein the reference voltage is an internallygenerated voltage.
 19. The semiconductor charge pump circuit of claim10, wherein an area ratio of the pair of capacitors is such thatvoltages across each capacitor are evenly distributed.